`include "ascon_define.v"

module `ASCON_AEAD_FINAL
(
    input                                        ascon_aead_clk_i,                      //其中a的含义为ascon_aead，代表该时钟域
    input                                        ascon_aead_rst_n_i,

    input                                        ascon_aead_final_vld_i,
    input                                        ascon_aead_final_en_i,
    input                                        ascon_aead_final_mode_i,
    input                             [`K_W-1:0] ascon_aead_final_k_i,
    input                             [`S_W-1:0] ascon_aead_final_s_i,

    output                            [`T_W-1:0] ascon_aead_final_t_o,
    output                                       ascon_aead_final_vld_o
);

//外信号

wire                                             vld_i_p;
wire                                             en_p;
wire                                  [`K_W-1:0] k_p;
wire                                  [`S_W-1:0] s_p;
wire                                             mode_p;
wire                                  [`T_W-1:0] t_p;
wire                                             vld_o_p;
//接口信号
wire                                  [`S_W-1:0] n_s_w;
wire                                  [`S_W-1:0] a_s_w;
wire                                  [`S_W-1:0] s_i_w;
wire                                  [`S_W-1:0] s_o_w;

//连接接口信号

assign vld_i_p                 = ascon_aead_final_vld_i;
assign en_p                    = ascon_aead_final_en_i;
assign k_p                     = ascon_aead_final_k_i;
assign s_p                     = ascon_aead_final_s_i;
assign mode_p                  = ascon_aead_final_mode_i;

assign ascon_aead_final_t_o         = t_p;
assign ascon_aead_final_vld_o       = vld_o_p;

//接口信号 生成

assign n_s_w            = s_p ^ {64'b0,k_p,128'b0};
assign a_s_w            = s_p ^ {128'b0,k_p,64'b0};
assign s_i_w            = (mode_p == 1'b0) ? a_s_w : n_s_w;
assign t_p              = s_o_w[`T_W-1:0] ^ k_p;

`P12
u_p12
(
     .clk_i                            (ascon_aead_clk_i                       ),
     .rst_n_i                          (ascon_aead_rst_n_i                     ),
     .p12_en_i                         (en_p                                   ),
     .p12_vld_i                        (vld_i_p                                ),
     .p12_s_i                          (s_i_w                                  ),
     .p12_s_o                          (s_o_w                                  ),
     .p12_vld_o                        (vld_o_p                                )
);



endmodule